The present disclosure relates in general to devices and methods for DRAM initialization. In particular, the present disclosure relates to devices and methods for DRAM initialization according to initialization parameters stored when DRAM are not removed.
Computers generally comprise a CPU, chipsets, a memory controller and buses. CPU processes most operations of the computer. Chipsets support the operation of the CPU. Generally, the chipset comprises controllers for transmission of data between the CPU and other devices. The memory controller is a part of the chipset, establishing data transmission between memory and the CPU. Buses are connected between the CPU, memory, and other I/O devices. The bus determines the operating speed of a main board. In response to different data transmission requirements, different kinds of buses are provided. A memory bus is connected between the memory controller and the memory module.
During boot, memory initialization is performed, comprising setting memory operating frequency and a column address strobe latency (CL).
Conventional technology obtains memory initialization parameters by reading serial presence detect (SPD) codes stored in EEPROM of the memory. Thereby, information required for memory initialization is obtained.
Using double data rate-synchronous DRAM (DDR) as an example, the operating frequency of the DDR can be 400 MHz, 333 MHz and 266 MHz, and column address strobe latency (CL) of the DDR can be 3 clocks, 2.5 clocks and 2 clocks. BIOS can initialize the DDR operating at 400 MHz and 2.5 CL according to SPD.
Boot is delayed by determination of the information required for initialization of memory, performed at each boot. However, when memory is not removed between consecutive boots, determination of the information for memory initialization at subsequent boot is unnecessary since determination is the same.